Integrated circuit with input/output pad having pullup or pulldown

ABSTRACT

Voltage pullup or pulldown devices of general purpose input/output pads of integrated circuit chips are controlled by signals derived from a core of the chip and which indicate (1) if the pad is to be enabled to output a value and (2) the value of the signal to be outputted. Such devices are controlled to supply different current levels to the input/output terminals as a function of whether the chip is operating in &#34;sleep&#34; and interrupt modes. The device of each pad is disabled when signals or commands are supplied via the pad from the chip to circuitry external to the chip and vice versa.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits havinginput/output terminals connected to input/output pads having voltagepullup or pulldown devices for the terminals and, more particularly, toan integrated circuit including such devices that are controlled bysignals derived from a core of the integrated circuit and which indicate(i) if the pad is to be enabled to output a value and (ii) the value ofthe signal to be outputted. Another aspect of the invention relates tointegrated circuits including such devices that are controlled to supplydifferent current levels to the input/output terminals in response tologic signals derived from the integrated circuit.

BACKGROUND ART

A common configuration for integrated circuits that perform binarysignal processing functions is illustrated in FIG. 1, wherein integratedcircuit chip 10 is illustrated as including core 12 containing the mainlogic area where the binary signal processing functions are performed.Signals are coupled from and into core 12 via N identical generalpurpose input/output pads 14, each connected to one of N input/outputpins 16, where N is an integer greater than 1 and typically has a valueof 16, 32, or more. Pads 14 are at the periphery of the chip andconnected via appropriate bonded leads to pins 16 fixedly connected atthe outer edges of a package (not shown) containing the chip. Since allof pads 14 are identical, the description proceeds with regard to asingle pad 14.

General purpose input/output pad 14 includes terminal 18 directlyconnected to pin 16. Terminal 18 is connected to a DC reference voltageat terminal 20 by device 22, which can be either a pullup or pulldowndevice; for ease of further description, it is assumed that device 22 isa pullup device which, when enabled, tends to maintain terminal 18 atthe positive DC voltage at terminal 20. When pullup device 22 isdisabled, terminal 18 is free to float and the voltage at terminal 18 iscontrolled by (1) the voltage supplied to the terminal from pin 16 whena signal is coupled to integrated circuit chip 10 via pin 16 or (2) thevoltage at the output of amplifier 24. Pullup device 22, when enabled,has a much greater impedance than the output impedance of amplifier 24or of the signal source external to chip 10, so the amplifier or theexternal source can overcome the pullup effects of device 22. When avoltage is supplied to terminal 18 from pin 16, the voltage at terminal18 is coupled to the input of amplifier 26, having an output coupled tocircuitry within core 12.

Core 12 includes addressable register 28 having three memory elements30, 32 and 34 for each of the N general purpose input/output pads 14.Other portions of core 12 load binary signal levels into memory elements30, 32 and 34. Memory element 30 stores a binary control signal levelindicative of whether pullup device 22 is enabled to couple the voltageat terminal 20 to terminal 18 or if pullup device 22 is to be disabled,in which case terminal 18 can float or is driven to a voltage at anoutput of a source supplying a signal to terminal 18. Memory element 32is loaded with a binary value indicative of whether input/output pad 14is to supply a binary 1 or 0 value to pin 16. In the logic set of theprior art discussed in connection with FIG. 1 and the preferredembodiment of the present invention as described in connection with theremaining figures, binary 1 and 0 values in element 34 are respectivelyassociated with low (ground) and positive (high) voltages, but it is tobe understood that other logic sets can be used. (The binary 1 and 0values of other binary signals are respectively associated with positivehigh and low (ground) voltages.) The value in storage element 32 isselectively coupled through amplifier 24 to terminal 18 under thecontrol of binary values loaded in memory element 34. To this end, thesignal in element 34 is supplied to inverting power supply terminal 36of tristate amplifier 24 so that when the signal in element 34 has a lowvoltage (associated with a binary 1 value) the amplifier is enabled andhas a low output impedance serving as a voltage source for a positive(binary 0 value) voltage and a low (binary 1 value) voltage determinedby the binary value of the signal in element 32. When a binary 3 is inelement 34, element 30 is usually loaded with a binary 0 to disablepullup device 22. When a binary 0 is in element 34, amplifier 24 isdisabled, has a high output impedance and an output voltage that isindependent of the binary signal in element 32.

with this prior art arrangement, the signals in storage elements 30 and34 both have binary 0 values to disable pullup device 22 and amplifier24 when a signal is supplied to pin 16 from circuitry external tointegrated circuit 10 so the voltage at terminal 18 is equal to thevoltage supplied to it from external circuitry via pin 16. In addition,pullup device 22 may be enabled for some types of input to pin 16 fromexternal sources, e.g., (1) if an external switch is tied to ground, (2)if an external signal is derived by an open drain device, and (3) if nosource is connected to the pin, so the pin would otherwise float. Whenamplifier 24 is disabled by the high voltage in storage element 34 andno signal is to be applied to pin 16 from external circuitry, terminal18 is maintained at the voltage of terminal 20 by enabling, i.e.activating, pullup device 22 by a high voltage (binary 1 value) instorage element 30.

While the prior art device functions adequately, we have realized thatthe prior art has the disadvantage of requiring an excess lead wire. Wehave realized it is not necessary to provide a separate lead wire fromstorage element 30 to pullup device 22 and that storage element 30 canbe eliminated for each input/output pad 14. Since register 28 is usuallyburied deep in core 12, elimination of the lead wire and of .storageelement 30 decreases the size of core 12 and therefore of the entireintegrated circuit chip 20. Elimination of these parts is significantwhen it is realized there are frequently 32 or more input/output pads.

we have also realized current and therefore power consumption can bereduced by decreasing the current supplied via the pullup devices duringcertain operating conditions of the core, particularly for a low power,i.e. sleep, mode of operation of the integrated circuit chip and/or whenthe integrated circuit chip is responsive to an externally derivedinterrupt signal.

It is, accordingly, an object of the present invention to provide a newand improved integrated circuit chip having a core for performing binarysignal processing functions as well as general purpose input/outputpads, wherein the volumetric requirements of the integrated circuit chipare reduced.

An additional object of the invention is to provide a new and improvedintegrated circuit chip including a core for performing binary signalprocessing functions in combination with a general purpose input/outputpad having a pullup or pulldown device that is controlled by the samesignals that control other components in the input/output pad so as toreduce the number of leads between the core and the input/output pad.

An additional object of the invention is to provide a new and improvedintegrated circuit having input/output pads including pullup or pulldowndevices that are operated at relatively low current levels when theintegrated circuit is operated under certain operating conditions, e.g.low power (sleep) and/or interrupt conditions.

THE INVENTION

Certain of these objects are achieved by providing an integrated circuitchip comprising N input/output pads, one for each of N pins of anintegrated circuit package in which the chip is to be located, whereinpad i has a first terminal adapted to be connected to pin i, where N isan integer greater than 1 and i is selectively 1 . . . N. Core circuitryfor performing binary signal processing functions includes circuitry forderiving a first binary signal having a level for determining the valueof an output bit to be coupled through pad i to the first terminal ofpad i and a second binary signal having a level for controlling whetheror not an output signal is to be coupled from pad i to circuitryexternal to the integrated circuit chip. Pad i includes a device forselectively pulling the first terminal of pad i to a voltage at a secondterminal in response to the levels of the first and second binarysignals for pad i, and further circuitry for causing the voltage at thefirst terminal of pad i to be at different predetermined voltagesrespectively associated with first and second binary values in responseto the first signal for pad i respectively signifying that the first andsecond binary values are to be coupled to pin i from the chip and thesecond signal for pad i signifying that pad i is to be enabled foroutputting a signal. The pulling device of pad i responds to the firstand second signals for (1) pulling the voltage at the first terminal ofpad i to the voltage at the second terminal to prevent floating of thefirst terminal of pad i when no signal is to be applied to the firstterminal of pad i by the further circuitry or by circuitry external tothe integrated circuit and (2) decoupling the first terminal of pad ifrom the second terminal so the voltage at the first terminal of pad iis not controlled by the voltaic at the second terminal when a signal isto be applied to the terminal of pad i from circuitry external to theintegrated circuit or by the further circuitry.

Other objects are achieved by providing an integrated circuit chipcomprising a core for performing binary signal processing functions andfor deriving binary output signals in combination with a pad at theperiphery of the chip connected to be responsive to the binary outputsignals and including a first terminal for supplying a signal tocircuitry external to the chip. The pad includes a device forselectively pulling the first terminal to a predetermined DC voltage ata second terminal. The device is connected between the first and secondterminals and is responsive to the binary output signals for supplyingcurrents i₁ and i₂ to the first terminal at different times and fordecoupling currents i₁ and i₂ from the first terminal so the voltage atthe first terminal is not controlled by either of the currents i₁ or i₂at other times, where i₁ >>i₂.

In certain embodiments one of the binary output signals derived by thecore has first and second values to respectively indicate the core isoperating in first and second modes. The device is connected to beresponsive to said one binary output signal to supply current i₂ fromthe second terminal to the first terminal when said one binary outputsignal indicates the core is operating in the first mode and toselectively supply current i₁ from the second terminal to the firstterminal when said one binary output signal indicates the core isoperating in the second mode. In a preferred embodiment, the modes arehigh and low power levels.

Further objects are achieved with an integrated circuit chip forperforming binary signal processing functions and deriving binary outputsignals. A pad at the periphery of the chip connected to be responsiveto the binary output signals includes a first terminal for supplying asignal to circuitry external to the chip. The pad includes a device forselectively pulling the first terminal to a predetermined DC voltage ata second terminal. The device is connected between the first and secondterminals and is responsive to the binary output signals for supplying acurrent from the second terminal to the first terminal and fordecoupling the first terminal from the second terminal so the voltage atthe first terminal is not controlled by the voltage at the secondterminal.

Circuitry on tho pad detects that an interrupt command has been coupledto the first terminal of the pad from circuitry external to the chip.The device is activated so the first terminal is decoupled from thesecond terminal, whereby the voltage at the first terminal is notcontrolled by the voltage at the second terminal when the chip isoperating in the interrupt mode as a result of the interrupt commandbeing coupled to the first terminal of the pad from circuitry externalto the chip. Thereby, the voltage at the first terminal is controlled bythe voltage associated with the interrupt command coupled to the firstterminal of the pad.

The above and still further objects, features and advantages of thepresent invention will become apparent upon consideration of thefollowing detailed descriptions of specific embodiments thereof,especially when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1, as described supra, is a circuit diagram of a prior artintegrated circuit including a core and input/output pads, each having apullup device;

FIG. 2 is a circuit diagram of an integrated circuit including onepreferred aspect of the invention, wherein a pullup device is controlledby signals representing the value of a binary level to be supplied to aninput/output terminal of the pad and a signal indicative of whether thepad is to be used for input or output purposes;

FIG. 3 is a circuit diagram of a modification of the circuit illustratedin FIG. 2 including provisions for changing the current in the pullupdevice to a relatively low level during low power operation of theintegrated circuit;

FIG. 4 is a circuit diagram of a pullup device which is particularlyadapted to be used in the circuit of FIG. 3; and

FIG. 5 is a modification of the circuit illustrated in FIG. 3,particularly adapted to be responsive to interrupt signals supplied bycircuitry external of the integrated circuit to a pin connected to apullup device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference is now made to FIG. 2 of the drawing, wherein the integratedcircuit chip illustrated in FIG. 1 is modified in accordance with oneaspect of the invention so register 28 includes, for each generalpurpose input/output pad 14, only two storage elements, namely storageelements 32 and 34 for respectively storing the output value to besupplied to terminal 18 and an indication as to whether input/output pad14 is to be activated to couple signals from integrated circuit 10 viaterminal 18 and pin 16 to circuitry external to the integrated circuitor if signals are to be coupled into core 12 from circuitry external ofthe integrated circuit via pin 16 and terminal 18. Thereby only twoleads 33 and 35 carry signals from core 12 of integrated circuit chip 10to each of input/output pads 14. While each of the pads includesadditional leads, the pads are at the periphery of integrated circuitchip 10 and the added leads on the pads do not have a material effect onthe size of the integrated circuit chip. Hence, storage element 30 andthe lead associated therewith for each of the N input/output pads 14 iseliminated to reduce the requirement for three leads to extend betweencore 12 and each of input/output pads 14, with resulting decreases inthe volumetric requirements of integrated circuit chip 10. The signalsin storage elements 32 and 34 are coupled to the input and power supplyterminals of amplifier 24 in the same manner described supra inconnection with the prior art of FIG. 1.

In FIG. 2, pullup device 40 is quite different from the prior art pullupdevice of FIG. 1. Pullup device 40 includes logic circuitry responsiveto the signals loaded by core 12 into memory elements 32 and 34, ascoupled to the pullup device. Logic circuitry in pullup device 40responds to the signals in memory elements 32 and 34 so that the pullupdevice is enabled only when plus (i.e., high) voltages are in both ofstorage elements 32 and 34. Because of the high impedance of pullupdevice 14, when enabled, the voltage at terminal 18 and pin 16 iscontrolled by the voltage of an external, low impedance active sourcedriving the pin or the voltage at terminal 20 if the external source isnot in an active state. Thereby floating of terminal 18 and pin 16 isprevented. For all other circumstances, pullup device 14 is disabled,whereby the voltage at terminal 18 (1) is controlled by the outputvoltage of amplifier 24 (when a low voltage is in element 34 to enablethe amplifier) as a function of the voltage in element 32 or (2) floats(when low and high voltages are respectively in elements 32 and 34 andno external source is supplying a signal to pin 16) or (3) is controlledby the voltage of the external source (when low and high voltages arerespectively in elements 32 and 34 and an external source is supplying asignal to pin 16). Thereby, terminal 18 and pin 16 rarely float and thevoltage thereof is stabilized under virtually all operating conditions.

As illustrated in FIG. 2, pullup device 40 includes normally cut-offfield effect transistor (FET) 41 having a source drain path connectedbetween terminals 18 and 20 and a gate electrode responsive to theoutput of NAND gate 43. Gate 43 includes non-inverting input terminals45 and 47 respectively responsive to the signals in storage elements 32and 34. Thereby, in response to the signals in elements 32 and 34respectively having high voltage values, the source drain path of FET 41is enabled and current flows from terminal 20 to terminal 18, to pullterminal 18 to the +V_(DD) DC voltage of terminal 20. Under all othercombinations of the signal values in elements 32 and 34, FET 41 is cutoff and the voltage at terminal 18 is not controlled by the voltage atterminal 20. The circuit of FIG. 2 thus operates and is constructed inthe same manner as the circuit of FIG. 1, except for the noteddifferences in operation and construction of pullup device 40 relativeto pullup device 22 of the prior art and that core 12 must supply binaryvalues to elements 32 and 34 to perform the functions provided by thebinary value in element 30.

Reference is now made to FIG. 3 of the drawing, a modification of thecircuitry illustrated in FIG. 2. The circuit of FIG. 3 is particularlyadapted to be used in conjunction with integrated circuit chips thatselectively operate in high and low power modes. To this end, core 12 ofintegrated circuit chip 10 includes conventional sleep signal source 42,which derives binary 1 and 0 levels (high and low voltages) to commandthe chip to operate in a low power, i.e., sleep, mode and a normalhigher power mode, respectively.

To reduce power when integrated circuit chip 10 is in the low poweroperating mode, the current, i₂, supplied to terminal 18 by the DCsource at terminal 20 to prevent terminal 18 from floating is reducedrelative to the current, i₁, which is supplied by terminal 20 toterminal 18 to prevent terminal 18 from floating when the chip is in ahigh power operating mode. For portable and plug-in integrated circuitchips, the advantages of reducing current, with associated powerreduction, are obvious. Low current can be tolerated at terminal 18 fromterminal 20 when chip 10 is in a low power state because the likelihoodof noise being supplied to terminal 18 at this time is significantlyreduced relative to when the chip is operating at high power. Fortypical high power operation of integrated circuit chip 10, the currentsupplied to terminal 18 by pullup device 22 or 40, is, e.g.,approximately 20 microamps. For typical low power operation of chip 10,the current supplied to terminal 18 by the pullup device of FIG. 3 isreduced significantly, e.g. to approximately 5 microamps.

To these ends, input/output pad 14 is modified to include parallelpullup devices 44 and 46, both driven in parallel by the signals fromstorage elements 32 and 34 and the output of sleep signal source 42.When enabled, pullup device 44 can supply only the low current levelfrom terminal 20 to terminal 18; when enabled, pullup device 46 cansupply only the high current level from terminal 20 to terminal 18. Inresponse to sleep signal source 42 deriving a binary 1 output level,indicative of integrated circuit chip 10 being in a low power state,pullup device 44 can be enabled to the exclusion of pullup device 46, Inresponse to sleep signal source 42 having a binary 0 level, indicativeof integrated circuit 10 being in a relatively high power operatingmode, pullup device 46 can be enabled to the exclusion of pullup device44. Pullup devices 44 and 46 respond to the signals in storage elements32 and 34 in the same manner that pullup device 40 responds to thesesignals. In addition, further control for pullup devices 44 and isprovided by the level of the signal derived from source 42. Generallywhen source 42 is deriving a binary 1, (high voltage) level, highvoltage values are respectively loaded by core 12 into elements 32 and

Reference is now made to FIG. 4 of the drawing, a circuit diagram ofpullup devices 44 and 46, in combination with terminals 20 and 18. Lowcurrent pullup device 44 and high current pullup device 46 respectivelyinclude normally cut-off FETs 48 and 58. When the FET 48 source drainpath is enabled it has a considerably higher resistance betweenterminals 18 and 20 than the source drain resistance of enabled FET 58;e.g. the resistance ratio is about 4:1. The relatively high and lowsource drain resistances of enabled FETs 48 and 58 are provided byproper design of the length to width ratios of the source drain paths ofthe PETs.

FET 48 is activated from the normally cut-off state to an enabledconducting state in response to a binary 0 being derived by NAND gate50, having an output connected to the gate electrode of PET 48. Gate 50includes non-inverting input terminals 52, 54 and 56 respectivelyconnected to be responsive to the outputs of sleep signal source 42, thebinary signal in storage element 32, and the binary signal in storageelement 34. Thus low power, i.e., weak, pullup device 44 is enabled andcurrent i₂ flows from terminal 20 to terminal 18 only when chip 10 is inthe sleep mode, a positive voltage is in element 32 and a positivevoltage is in element 34 to disable amplifier 24. If external circuitrysupplies a signal to pin 16 while chip 30 is in the low power mode, thesignal has sufficient current to overcome the effect of weak pullupdevice 44 and is coupled to core 12 to remove chip 10 from the sleepstate.

FET 58 includes a gate electrode connected to be responsive to theoutput of NAND gate 60. Gate 60 includes inverting input terminal 62 andnon-inverting input terminals 64 and 66, respectively connected to beresponsive to the output signal of source 42, the signal in element 32and the signal in element 34. The source drain path of FET 58 isactivated from its normally disabled state to an enabled state only inresponse to the voltage levels at terminals 62, 64 and 66 respectivelyhaving values of low, high and high values. Thus, high power, i.e.,strong, pullup device 46 is enabled and current i₁ flows from terminal20 to terminal 18 only when chip 10 is in a normal (non-sleep) mode, ahigh voltage is in element 32 and a high voltage is in element 34 todisable amplifier 24.

When the source drain path of either of FETs 48 or 58 is enabled, thevoltage at terminal. 18 does not float with respect to the voltage atterminal 20. Conversely, when the source drain paths of FETs 48 and 58are both disabled, the voltage at terminal 18 is driven to a binaryvalue determined by active signal sources which are external tointegrated circuit 10 and connected to terminal 18 or by the output ofamplifier 24.

According to a further aspect of the invention, illustrated in FIG. 5,power consumption of integrated circuit 10 is also reduced in responseto an interrupt signal being supplied by an external circuit via pin 16of at least one general purpose input/output pad 14 to integratedcircuit 10. Interrupt signals from circuitry external to integratedcircuit 10 have an active state as a result of a negative goingtransition from a normal positive DC level to a low voltage. In responseto the interrupt signal being supplied to pin 16 of a particularinput/output pad 14, a negative going leading edge thereof is detectedby circuitry in the input/output pad, causing the pullup device of thatpad to be disabled so the voltage at terminal 18 of that pad is held atthe voltage associated with the interrupt command, while the chip is inthe low power mode. While this feature could be performed in the highpower mode, there is little advantage in disabling the pullup device forthe short duration while chip 10 is in the interrupt mode simultaneouslywith the chip being in the high power mode. While chip 10 is in the lowpower mode, weak and strong pullup devices 70 and 90 on the pad whichresponded to the externally derived interrupt are maintained in adisabled state until the interrupt signal is no longer being supplied tothe pad by the external interrupt source.

Device 70 differs somewhat from low power (weak) pullup device 44 (FIG.4) while strong pullup device 90 is the same as strong pullup device 46,so no further description thereof is necessary. Pullup device 70includes FET 71 that corresponds with PET 48 of pullup device 44. Thepad illustrated in FIG. 5 is responsive to an interrupt command sourcederived from an external source, as coupled to terminal 18 via pad 16,but it is not necessary for all of the input/output pads on integratedcircuit chip 10 to be responsive to externally derived interrupt commandsources.

The negative going leading edge and positive going trailing edge of theinterrupt pulse coupled to pin 16 by circuitry external to integratedcircuit chip 10 are detected by flip-flop 72, connected to the output ofamplifier 26. Flip-flop 72 includes inverting set (S), non-invertingreset (R), and inverting clear (CLR) input terminals, as well as Qoutput terminal. The inverting set and reset input .terminals offlip-flop 72 are connected in parallel to the output of amplifier 26 sothe flip-flop is respectively driven to the set and reset states bynegative going leading and positive Going trailing edges of theinterrupt signal from an external source. The inverting clear inputterminal of flip-flop 72 is connected to sleep source 42 so theflip-flop is in the reset state when chip 10 is in the normal, non-sleepmode. The Q output terminal of flip-flop 72 is connected to invertinginput terminal 74 of NAND gate 76 having non-inverting input terminals78 and 80 respectively connected to elements 32 and 34. The gateelectrode of normally cut off FET 71 in low power (weak) pullup device70 is connected to be responsive to the output of NAND gate 82.

In response to a negative going transition associated with the beginningof an interrupt command being supplied by an external circuit to pin 16while the sleep signal has a binary 1 value, flip-flop 72 is set, soNAND gate 76 cannot enable FET 71 of weak pullup device 70.Simultaneously, strong pullup device 90 is disabled because the binary 1output of sleep indicating source 42 supplied to inverting inputterminal 62 of AND gate 60 causes gate 60 to apply a binary 0 to thegate electrode of FET 58 to cut off the FET., Thus, no current flowsbetween terminals 18 and 20, whereby the voltage at terminal 18 is notcontrolled by the voltage at terminal 20 but is maintained at thevoltage supplied to pin 16 by the interrupt source.

When chip 10 is in the high power mode, the negative going transition atthe inverting set input of flip-flop 88 has no effect on weak pullupdevice 70 because source 42 is applying a low voltage to the invertingclear input of the flip-flop to prevent enabling of weak pullup device70.

When the interrupt source external to chip 10 has terminated while thechip is in the sleep mode, the resulting positive going transition atthe non-inverting reset (R) input of flip-flop 88 resets the flip-flopso NAND gate 76 can be controlled by the signals in elements 32 and 34.Elements 32 and 34 are respectively programmed to store high voltageswhile sleep source 42 is deriving a binary 1 value. NAND gate 82 therebysupplies a binary 1 level to the gate electrode of FET 71 to enable weakpullup device 70 so terminal 18 and pin 16 are pulled up to the positiveDC voltage at terminal 20 to prevent the pin and terminal 18 fromfloating. Pullup device 70 remains in this state until there is a changein the state of signal source 42 or an interrupt is again applied to pin16 from the external source. The interrupt from the external sourceovercomes the effect of weak pullup device 70 because the externalsource has a much lower output impedance than the source drainresistance of FET 71 when the FET is enabled and supplies much morecurrent to terminal 18 than is supplied to this terminal via the sourcedrain path of FET 71. The negative going leading edge of the interruptdisables weak pullup device 70, as described supra, as does a change inthe value of the signal derived from source 42.

While there have been described and illustrated several specificembodiments of the invention, it will be clear that variations in thedetails of the embodiments specifically illustrated and described may bemade without departing from the true spirit and scope of the inventionas defined in the appended claims. For example, both of the parallelFETs forming the pullup devices of FIGS. 4 and 5 can be enabled duringstrong pullup operation with appropriate change in the logic of thesefigures.

What is claimed:
 1. An integrated circuit chip comprising N input/outputpads, one for each of N pins of an integrated circuit package in whichthe chip is to be located, pad i having a first terminal, the firstterminal of pad i adapted to be connected to pin i, where N is aninteger greater than 1 and i is selectively 1 . . . N, core circuitryfor performing binary signal processing functions, the core circuitryincluding circuitry for pad i for deriving a first binary signal havinga level for determining the value of an output bit to be coupled throughthe pad to the first terminal of pad i and a second binary signal havinga level for controlling whether or not an output signal is to be coupledfrom pad i to circuitry external to the integrated circuit chip; pad iincluding a device for selectively pulling the first terminal of pad ito a voltage at a second terminal in response to the levels of the firstand second signals for pad i; further circuitry for causing the voltageat the first terminal of pad i to be at different predetermined voltagesrespectively associated with first and second binary values in responseto the first signal for pad i respectively signifying that the first andsecond binary values are to be coupled to pin i from the chip and thesecond signal for pad i signifying that pad i is to be enabled foroutputting a signal; the pulling device of pad i responding to the firstand second signals for (1) pulling the voltage at the first terminal ofpad i to the voltage at the second terminal to prevent floating of theterminal of pad i when no signal is to be applied to the first terminalof pad i by the further circuitry or by circuitry external to theintegrated circuit and (2) decoupling the first terminal of pad i fromthe second terminal so the voltage at the first terminal of pad i is notcontrolled by the voltage at the second terminal when a signal is to beapplied to the terminal of pad i from circuitry external to theintegrated circuit or by the further circuitry.
 2. The integratedcircuit chip of claim 1 wherein the core circuitry includes a signalsource for selectively causing the chip to operate at high and low powermodes, the device of pad i including circuitry responsive to the highand low power modes signal source for supplying a lower current to theterminal of pad i when the low power operating mode is signalled thanwhen the high power operating mode is signalled when the voltage at thefirst terminal of pad i is pulled to the voltage at the second terminal.3. The integrated circuit chip of claim 2 wherein the circuitry of pad iresponsive to the signal source for the high and low power modesincludes first and second parallel devices for selectively pulling thefirst terminal of pad i to the voltage at the second terminal, the firstdevice having a larger resistance than the second device and beingselectively enabled when the low power mode is signalled, the seconddevice being selectively enabled when the high power mode is signalledand being incapable of being enabled when the low power mode issignalled.
 4. The integrated circuit chip of claim 2 wherein one of thepads includes a detector for predetermined voltage variations coupled tothe first terminal of the one pad from circuitry external to theintegrated circuit, the detector responding to the predetermined voltagevariations for disabling the device of the one pad so the voltage at thefirst terminal of the one pad is not controlled by the voltage at thesecond terminal.
 5. The integrated circuit chip of claim 4 furtherincluding circuitry for selectively causing the device to be re-enabledso the voltage at the first terminal of pad i can be selectivelycontrolled by the voltage at another terminal after a signal associatedwith the voltage variations has been recognized by the core circuitry ashaving been terminated.
 6. The integrated circuit chip of claim 1wherein the chip is included in an integrated circuit package includingthe N pins.
 7. The integrated circuit chip of claim 1 wherein one of thepads includes a detector for predetermined voltage variations coupled tothe first terminal of the one pad from circuitry external to theintegrated circuit, the detector responding to the predetermined voltagevariations for disabling the device of the one pad so the voltage at thefirst terminal of the one pad is not controlled by the voltage at thesecond terminal.
 8. The integrated circuit chip of claim 7 furtherincluding circuitry for selectively causing the device to be re-enabledso the voltage at the first terminal of pad i can be selectivelycontrolled by the voltage at another terminal after a signal associatedwith the voltage variations has been recognized by the core circuitry ashaving been terminated.
 9. An integrated circuit chip comprising a corefor performing binary signal processing functions and for derivingbinary output signals, a pad at the periphery of the chip connected tobe responsive to the binary output signals and including a firstterminal for supplying a signal to circuitry external to the chip, thepad including a device for selectively pulling the first terminal to apredetermined DC voltage at a second terminal, the device beingconnected between the first and second terminals and being responsive tothe binary output signals for supplying currents i₁ and i₂ to the firstterminal at different times and for decoupling currents i₁ and i₂ fromthe first terminal so the voltage at the first terminal is notcontrolled by either of the currents i₁ or i₂ at other times, where i₁>>i₂ ;wherein one of the binary output signals derived by the core hasfirst and second values to respectively indicate the core is operatingin high and low power modes, said device being connected to beresponsive to said one binary output signal to supply current i₂ fromthe second terminal to the first terminal when said one binary outputsignal indicates the core is operating in the low power mode and toselectively supply current i₁ from the second terminal to the firstterminal when said one binary output signal indicates the core isoperating in the high power mode.
 10. The integrated circuit chip ofclaim 9 wherein the chip includes circuitry for detecting than aninterrupt command has been coupled to the first terminal of the pad fromcircuitry external to the chip, the device being activated so the firstterminal is decoupled from the second terminal so the voltage at thefirst terminal is not controlled by the voltage at the second terminalwhen the core is operating in the interrupt mode as a result of theinterrupt command being coupled to the first terminal of the pad fromcircuitry external to the chip and the voltage at the first terminal iscontrolled by the voltage associated with the interrupt command coupledto the first terminal of the pad.
 11. The integrated circuit chip ofclaim 10 wherein the circuitry for detecting that an interrupt commandhas been coupled to the first terminal of the pad from circuitryexternal to the chip is on the pad.
 12. The integrated circuit chip ofclaim 9 wherein the chip includes circuitry for detecting that aninterrupt command has been coupled to the first terminal of the pad fromcircuitry external to the chip, the device being activated so the firstterminal is decoupled from the second terminal so the voltage at thefirst terminal is not controlled by the voltage at the second terminalwhen the core is operating in the interrupt mode as a result of theinterrupt command being coupled to the first terminal of the pad fromcircuitry external to the chip and the voltage at the first terminal iscontrolled by the voltage associated with the interrupt command coupledto the first terminal of the pad.
 13. The integrated circuit chip ofclaim 12 wherein the circuitry for detecting that an interrupt commandhas been coupled to the first terminal of the pad from circuitryexternal to the chip is on the pad.
 14. An integrated circuit chipcomprising a care for performing binary signal processing functions andfor deriving binary output signals, a pad at the periphery of the chipconnected to be responsive to the binary output signals and including afirst terminal for supplying a signal to circuitry external to the chip;the pad including a device for selectively pulling the first terminal toa predetermined DC voltage at a second terminal, the device beingconnected between the first and second terminals and being responsive tothe binary output signals for supplying a current from the secondterminal to the first terminal and for decoupling the first terminalfrom the second terminal so the voltage at the first terminal is notcontrolled by the voltage at the second terminal, a detector fordetecting that an interrupt command has been coupled to the firstterminal of the pad from circuitry external to the chip, and circuitryresponsive to the detector for activating the device so the firstterminal is decoupled from the second terminal so the voltage at thefirst terminal is not controlled by the voltage at the second terminalwhen the chip is operating in the interrupt mode as a result of theinterrupt command being coupled to the first terminal of the pad fromcircuitry external to the chip and the voltage at the first terminal iscontrolled by the voltage associated with the interrupt command coupledto the first terminal of the pad.
 15. The integrated circuit chip ofclaim 14 wherein the pad includes the detector and circuitry.